منابع مشابه
Rapid prototyping of self-timed circuits
Self-timed circuits relieve the designer of problems like clock distribution, but introduce new constraints in the form of isochronic forks and equipotential regions. This paper shows how the combination of floorand geometryplanning tools can be used to address these new problems. As a result, prototype self-timed circuits can be developed on conventional, clocked FPGAs without sacrificing perf...
متن کاملSpecification and analysis of self-timed circuits
The problems of self-timed behavior specification and verification are considered on the basis of an event model-Change Diagram (CD). The descriptive power of a CD model is demonstrated by comparing the CD with Signal Transition Graphs (STG). CD differs from STG by two types of causal relations (AND and OR) between events (in STG only AND-relation is presented). CD verification is shown to be r...
متن کاملSelf-Timed Design with Dynamic Domino Circuits
We introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the pre-charge/evaluate c...
متن کاملOptimization of NULL convention self-timed circuits
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of four or fewer variables, thus facilitating a variety of gatelevel optimizations. TCR optimizations are formalized for NCL and then assessed by c...
متن کاملSelf-timed and speed independent latch circuits
Several designs of self-timed (some of which speed independent) latch circuits are presented. These are used in the speed independent (SI) implementation of two consecutive binary assignment statements. Issues such as logic reduction, utilisation of well known, simple components, and response speed improvement are dealt with in detail. The techniques employed can be used in designing other asyn...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2019
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2018.2884881